FIG. 19 is a sectional view illustrating a conventional planar FET. In the figure, reference numeral 1 designates a semi-insulating GaAs substrate with a (100) surface orientation. A gate electrode 3 comprising WSi is disposed on a part of the GaAs substrate 1. An n type GaAs active region 2 is disposed within the GaAs substrate 1 and lies at the surface where the gate electrode 3 is disposed. Relatively low impurity concentration n type GaAs regions 4 are disposed at opposite sides of the active region 2. Relatively high impurity concentration n type GaAs source and drain regions 5 are disposed at opposite sides of the relatively low impurity concentration regions 4. Source and drain electrodes 6 and 7 comprising AuGe/Ni/Au are disposed on the source and drain regions 5, respectively. A passivation film comprising SiON, SiO, SiN, or the like is disposed on the entire surface of the structure.
FIGS. 20(a)-20(e) illustrate a method for producing the planar FET of FIG. 19.
Initially, the n type GaAs active region 2 is formed in the semi-insulating GaAs substrate 1 by ion implantation (FIG. 20(a)). Then, WSi is deposited over the substrate by sputtering and a photoresist pattern is formed thereon. Using the photoresist pattern as a mask, the WSi film is etched by reactive ion etching, forming the WSi gate electrode 3 (FIG. 20(b)).
Using the WSi gate 3 as a mask, Si ions are implanted at energy of 50 KeV and dosage of 2.times.10.sup.12 cm.sup.-2 forming the relatively low ion concentration n type GaAs regions 4 (FIG. 20(c)).
Then, an SiO film is deposited over the entire surface of the wafer. The SiO film is anisotropically etched by reactive ion etching using a gas mixture of CHF.sub.3 /O.sub.2, forming side walls 9 on opposite sides of the WSi gate 3.
Using the WSi gate 3 with the side walls 9 as a mask, Si ions are implanted at energy of 60 KeV and dosage of 3.times.10.sup.13 cm.sup.-2 followed by removal of the side walls 9 using BHF (buffered hydrofluoric acid) and annealing at 800.degree. C. for 30 minutes, forming the relatively high ion concentration source and drain regions 5. If the insulating side walls 9 remain on the GaAs substrate during the annealing process, the side walls 9 unfavorably act on the GaAs substrate to produce Ga and As atom vacancies in the substrate and a current leakage layer at the interface between the side walls and the substrate, adversely affecting the FET characteristics. Therefore, the side walls 9 must be removed before the annealing process.
Thereafter, the source and drain electrodes 6 and 7 comprising AuGe/Ni/Au are formed by conventional deposition and lift-off techniques (FIG. 20(e)). Finally, an insulating film, such as SiN, SiON, or SiO, is deposited over the wafer to form the passivation film 21, completing the structure of FIG. 19.
FIG. 21 is a sectional view illustrating a conventional FET having a recessed gate structure. In the figure, reference numeral 1 designates a semi-insulating GaAs substrate having a (100) surface orientation. An n type GaAs active layer 15 having a recess is disposed on the GaAs substrate 1. A gate electrode 16 comprising Ti/Pt/Au is disposed in the recess. Source and drain electrodes 6 and 7 are disposed on the active layer 15 spaced apart from each other. An insulating film 24 is disposed on the whole surface of the structure.
A method for fabricating the FET of FIG. 21 is illustrated in FIGS. 22(a)-22(d).
Initially, as illustrated in FIG. 22(a), the n type GaAs active layer 15 is formed in the semi-insulating GaAs substrate 1 by ion implantation. Alternatively, the active layer may be epitaxially grown on the surface of the substrate by MBE (Molecular Beam Epitaxy) or MOCVD (Metalorganic Chemical Vapor Deposition). Then, the source and drain electrodes 6 and 7 comprising AuGe/Ni/Au are formed on the active layer 15 by conventional deposition and lift-off techniques (FIG. 22(b)).
Using a photoresist mask 23 with an opening opposite a region where a gate electrode is to be formed, the active layer 15 is etched with a mixture of tartaric acid and hydrogen peroxide to form a recess 15a (FIG. 22(c)).
Then, Ti/Pt/Au is deposited by sputtering using the photoresist mask 23. The photoresist mask 23 and overlying portions of the metal are removed by lift-off, forming the gate electrode 16 in the recess 15a. Finally, an insulating film, such as SiN, SiON, or SiO, is deposited over the entire surface of the wafer to form the passivation film 23, completing the structure of FIG. 21.
A description is given of transient response characteristics of a drain current when a pulse voltage is applied to the gate electrode of the above-described recessed-gate type GaAs FET. FIG. 23 schematically shows the transient response delay of the drain current in response to a pulsed gate voltage and FIG. 24 schematically shows the mechanism of the transient response delay.
As shown in FIG. 23, when a pulse voltage having a pulse width in a range from several .mu.sec to several msec and an amplitude for turning on or off the channel is applied to the gate electrode of the conventional FET, although there is no delay in the drain current in responding to the gate voltage at the pulse decay time (channel OFF time), there is a delay in the drain current to the gate voltage at the pulse rise time (channel ON time). There are various arguments about this delay mechanism, but no definite explanation has been given yet. In "Modeling the Effects of Surface States on DLTS Spectra of GaAs MESFET's" (IEEE Transactions on Electron Devices, Vol.37, No.5, p.1235, 1990) and "Numerical Simulation of GaAs MESFET Gate-Lag with a Surface State Model" (Transactions of Electronic Information Communication Society, ED-91-142, p.25, 1992), variation in thickness of the surface depletion layer due to the capture and emission of electrons by the surface states on a region of the GaAs surface between the drain electrode and the gate electrode is thought to be an important factor of the delay mechanism. The delay mechanism will be described in more detail referring to FIG. 24. In FIG. 24, the drain voltage (Vds) is 5 V, the gate OFF voltage is -5 V, and the gate 0N voltage is 0 V.
When the gate is in its ON state with the source-to-gate voltage of 0 V and the gate-to-drain voltage of -5 V, the surface states between the valence band and the Fermi level or the quasi Fermi level at the GaAs surface produced by this potential capture electrons. When -5 V is applied to the gate to turn off the gate, the quasi Fermi level at the surface approaches the conduction band and the surface states between the valence band and the quasi Fermi level increase, whereby the quantity of electrons captured by the surface states increases as compared with that in the ON state. The increase in the electrons captured by the surface states increases the positive electric charges, i.e., donors, within the substrate required to maintain electrical neutrality, resulting in an expanded surface depletion layer.
When 0 V is applied to the gate to turn on the gate, the quasi Fermi level at the surface approaches the valence band and the surface states between the conduction band and the quasi Fermi level emit electrons, whereby the quantity of electrons captured by the surface states decreases as compared with in the OFF state. The decrease in the electrons captured by the surface states decreases the positive electric charges, i.e., donors, within the substrate required to maintain electrical neutrality, resulting in a thin surface depletion layer.
As described above, the thickness of the surface depletion layer varies according to the electron capture and emission of the surface states. In case of the n type GaAs substrate, the time constant of the electron emission is much longer than that of the electron capture and, therefore, the reduction in the surface depletion layer at the gate ON time does not catch up with the reduction in the depletion layer beneath the gate electrode, resulting in the depletion layer between the ohmic electrode and the gate electrode being larger than the depletion layer beneath the gate electrode.
The drain current Id is qualitatively represented by the following formula: EQU Id.varies.(R.sub.ch +R.sub.1 (.tau.)+R.sub.2 (.tau.)).sup.-1
where Rch is the intrinsic channel resistance, and R.sub.1 (.tau.) and R.sub.2 (.tau.) are resistances in regions narrowed by the surface depletion layers. It is understood from this formula that the channel narrowing due to the surface depletion layer reduces the drain Current and, particularly when the resistances R.sub.1 (.tau.) and R.sub.2 (.tau.) have time constants larger than the time constant of the intrinsic channel resistance R.sub.ch at the gate ON time, the pulse rise time of the drain current is delayed.
This phenomenon is seen in the conventional planar FET as shown in FIG. 25.
Since the delay in the pulse rise time of the drain current is caused by the channel narrowing due to the surface depletion layer, in order to reduce the delay, it is necessary to decrease the surface depletion layer or to make a structure in which channel narrowing due to the surface depletion layer hardly occurs.
As a structure for preventing channel narrowing, a two-stage recessed gate structure is disclosed in "Gate Slow Transients in GaAs MESFETs--Causes, Cures, AND Impact on Circuits", IEEE IEDM, p. 842, 1988, and a structure with an intrinsic type GaAs layer on a channel layer is disclosed in "Step-Recessed Gate Structure with an Undoped Surface Layer for Microwave and Milimeter-wave High Power, High Efficiency GaAs MESFETs" IEICE Transactions, Vol. E74, No. 12, 4141, 1991. However, these recessed-gate FETs are complicated in structure and production. In addition, no effective countermeasure to the delay in the drain current is reported with respect to the planar FET.
Since the thickness of the surface depletion layer is determined by the density of the GaAs surface states and the surface potentials pinned by the surface states, it is thought that the thickness of the surface depletion layer is reduced by reducing the density of the surface states and increasing the donor concentration of the substrate.
Although a surface treatment using ammonium sulfide or the like is proposed for reducing the density of the surface states, such a treatment adversely affects thermal stability in subsequent processing and has no definite effect on the delay in the drain current.
On the other hand, the increase in an donor concentration of the substrate to reduce the surface depletion layer has the following drawbacks. In the conventional recessed-gate FET, after forming the n type GaAs layer by ion implantation or epitaxial growth, the recess etching is carried out to attain a desired thickness of the active layer and then the gate electrode is formed in the recess. Therefore, the donor concentration in a region under the gate electrode is equivalent to the donor concentration in a region between the gate electrode and the source and drain electrodes as shown in FIG. 21. Since the donor concentration of the channel is determined by the intended use of the transistor, lower donor concentration causes larger delay in the pulse rise time of the drain current.
In the conventional planar FET, in order to suppress the short channel effect, the n type GaAs regions 4 having a donor concentration higher than that of the active region 2 are disposed between the active region and the relatively high donor concentration regions 5 as shown in FIG. 19. Since the donor concentration of the regions 4 is optimized for the short channel effect, the gate breakdown voltage, and the source resistance, it is impossible to increase the donor concentration of the regions 4 for the purpose of suppressing the delay in the pulse rise time of the drain current.
In the above-described conventional FETs, the variation in the thickness of the depletion layer created between the gate electrode and the ohmic electrodes does not catch up with the variation in the thickness of the depletion layer created under the gate electrode, resulting in a delay in the pulse rise time of the drain current.